`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:       James Forrest
// 
// Create Date:    03:28:45 04/27/2013 
// Design Name: 
// Module Name:    comp 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module comp(input  signed[31:0] a, b,
			input  [4:0]  rt,
            input  [2:0]  compcont,
            output reg    result);

    always@(*)
	    case(compcont)
		    3'b000: result <= #1 (a[31] != rt[0]);  // bltz/bgez
			3'b001: result <= #1 (a == b);          // beq
			3'b101: result <= #1 (a != b);          // bne
			3'b010: result <= #1 (a <= 0);          // blez
			3'b110: result <= #1 (a > 0);           // bgtz
			default: result <= #1 1'bx;             // ???
		endcase
endmodule
